Software Developers Hpet Spec 1 0a – Download as PDF File .pdf), Text File .txt ) or read online. Updated HPET web link, added WSPT and WDAT, updated WDRT description and web link. Clarified that the endian-ness of data value. High Precision Event Timer Driver for Linux The High Precision Event Timer ( HPET) hardware follows a specification by Intel and Microsoft, revision 1.

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It consists of usually bit main counter which counts upas well as from 3 to 32 32 or 64 bit wide comparators. Keep in mind you have to initialize both the main counter and all of the comparators. Also, the routing as well as allowed routing of comparator interrupts is independent, so you have to detect and set it up for each of them individually.

More information on this procedure is provided further in the text. HPET offers two operating modes: In non-periodic mode, the OS programs one of timer’s comparator registers with value of main counter that is to trigger an interrupt. If the timer is set to 32 bit mode, it will also generate an interrupt when the counter wraps around. The comparator register’s value is never written by the hardware, you are free to write to it and read from it at any time, therefore you can change at what value in the main counter the interrupt will be generated.

Periodic mode is more tricky than non-periodic mode.

For periodic mode, similarly to one-shot mode, you write a value at which an interrupt shall be generated to the comparator register. When the interrupt is generated, however, the hardware will increase the value in comparator register by the last value written to it!

This is a consequence of HPET’s main counter being up-counting. So, if the main counter’s value is when we set the timer speclfication, and we write to comparator i.


There are two techniques to deal with this problem; they will both be described in later part of the article.

Comparators are NOT required to support this mode; you must detect this capability when initializing a comparator.

More information on this is provided further in the article. HPET supports three interrupt mapping options: In standard mapping, each timer has its own interrupt routing control.

This mapping mode will not be further discussed in this article. The following table and field descriptions can also be found in the specification. The following table skips reserved registers defined in the specification. hpett

When a corresponding timer interrupt is active, this bit is set. If it is set, software can clear it by writing 1 to this bit.

High Precision Event Timer

Writes of 0 have no effect. Reads will return current value of the main phet. If 32 bit reads are performed on 64 bit counter, consult 2.

It is recommended to use 32 bit counter when on bit only software. If another specificaion occurs before that bit is cleared, the interrupt will remain active. The following is the procedure you need to perform to initialize main counter and comparators in order to receive interrupts. Save minimal tick either from ACPI table or configuration register.

Support High Precision Event Timer (HPET) on x86 guests — Nova Specs documentation

Determine if timer N is periodic capable, save that information to avoid re-reading it every time. Determine allowed interrupt routing for current timer and allocate an interrupt for it. I am enabling the timers only when I actually use them, so there’s no “real” initialization of comparators here. Keep in mind that allowed interrupt routing may be insane.

Namely, you probably want to use some of ISA interrupts – or, at specificaiton least, be able to use them at one point unambiguously. Be aware of this when choosing interrupt routing for timers. I hope the above code is obvious. If it’s not, please analyze the meaning of specific fields in registers used above. Bit 2 is the same as above, Interrupt Enable. Bit 3 is also quite straightforward – 1 means periodic timer. But we’ve also set bit 6. This means specificatiob next write to timer N comparator register will have the usual meaning, while second next write will write directly to the accumulator.


I believe that the wording could’ve been much better. This page is not meant as a full description of HPET, only as a lightweight introduction. If you need any information not covered by this article, consult the HPET specification. Retrieved from ” https: Common Devices Interrupts Time.

Personal tools Log in. Views Read View source View history. About This site Joining Editing help Recent changes. This page was last modified on 31 Octoberat This page has been accessed 35, times. Must not be zero, must be less or equal to 0x05F5E, or nanoseconds. The functionality is dependent of whether edge or level-triggered mode is used for timer n.

It is always set to 0. Timer n Interrupt Routing Capability. If an illegal value is written, then value read back from this field will not match the written value. For bit timer, if this field is set, the timer specificatiin be forced to work in bit mode.

Otherwise it has no effect. This field is used to allow software to directly set periodic timer’s accumulator. Detailed explanation is provided further in the article. Otherwise, this bit will be ignored and reading it will always return 0. Setting this bit to 1 enables triggering of interrupts.